

The hardware subsequently implements stronger resiliency methods (e.g., redundant execution) only for crucial code.
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At the software level, the project is developing methods to classify crucial versus non-crucial code regions in a program: the crucial code affects program correctness and outcome, its functionality cannot be altered in any way non-crucial code affects program accuracy, therefore it could tolerate errors. The strategy focuses on data analytic applications since they naturally offer tradeoffs in program accuracy due to the unstructured nature of inputs, and the approximate algorithms used to solve these otherwise intractable problems. This project proposes a new method to achieve efficient resiliency, where hardware's coverage is bounded with certain guarantees, while computational efficiency is traded off at the cost of affecting program accuracy. These trends motivate the need for system resiliency without increasing power consumption. Further, with increasingly strict power constraints, hardware designs are now reliant on dynamic voltage scaling between nominal and near-threshold regions, which exacerbates the reliability problem.

With semiconductor technology scaling to sub-nanometer scales, minute perturbations in lithography patterns and manufacturing processes make the computing hardware vulnerable to unpredictable deviations in functionality.

Primary Place of Performance Congressional District:Ġ1001516DB NSF RESEARCH & RELATED ACTIVIT

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